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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">ID_MMFR3, Memory Model Feature Register 3</h1><p>The ID_MMFR3 characteristics are:</p><h2>Purpose</h2>
        <p>Provides information about the implemented memory model and memory management support in AArch32 state.</p>

      
        <p>For general information about the interpretation of the ID registers see <span class="xref">'Principles of the ID scheme for fields in ID registers'</span>.</p>
      <h2>Configuration</h2><p>AArch32 System register ID_MMFR3 bits [31:0] are architecturally mapped to AArch64 System register <a href="AArch64-id_mmfr3_el1.html">ID_MMFR3_EL1[31:0]</a>.</p><p>This register is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to ID_MMFR3 are <span class="arm-defined-word">UNDEFINED</span>.</p><h2>Attributes</h2>
        <p>ID_MMFR3 is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="4"><a href="#fieldset_0-31_28">Supersec</a></td><td class="lr" colspan="4"><a href="#fieldset_0-27_24">CMemSz</a></td><td class="lr" colspan="4"><a href="#fieldset_0-23_20">CohWalk</a></td><td class="lr" colspan="4"><a href="#fieldset_0-19_16">PAN</a></td><td class="lr" colspan="4"><a href="#fieldset_0-15_12">MaintBcst</a></td><td class="lr" colspan="4"><a href="#fieldset_0-11_8">BPMaint</a></td><td class="lr" colspan="4"><a href="#fieldset_0-7_4">CMaintSW</a></td><td class="lr" colspan="4"><a href="#fieldset_0-3_0">CMaintVA</a></td></tr></tbody></table><h4 id="fieldset_0-31_28">Supersec, bits [31:28]</h4><div class="field">
      <p>Supersections. On a VMSA implementation, indicates whether Supersections are supported. Defined values are:</p>
    <table class="valuetable"><tr><th>Supersec</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Supersections supported.</p>
        </td></tr><tr><td class="bitfield">0b1111</td><td>
          <p>Supersections not supported.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the permitted values are <span class="binarynumber">0b0000</span> and <span class="binarynumber">0b1111</span>.</p></div><h4 id="fieldset_0-27_24">CMemSz, bits [27:24]</h4><div class="field">
      <p>Cached Memory Size. Indicates the physical memory size supported by the caches. Defined values are:</p>
    <table class="valuetable"><tr><th>CMemSz</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>4GB, corresponding to a 32-bit physical address range.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>64GB, corresponding to a 36-bit physical address range.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>1TB or more, corresponding to a 40-bit or larger physical address range.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the permitted values are <span class="binarynumber">0b0000</span>, <span class="binarynumber">0b0001</span>, and <span class="binarynumber">0b0010</span>.</p></div><h4 id="fieldset_0-23_20">CohWalk, bits [23:20]</h4><div class="field">
      <p>Coherent Walk. Indicates whether Translation table updates require a clean to the Point of Unification. Defined values are:</p>
    <table class="valuetable"><tr><th>CohWalk</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Updates to the translation tables require a clean to the Point of Unification to ensure visibility by subsequent translation table walks.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Updates to the translation tables do not require a clean to the Point of Unification to ensure visibility by subsequent translation table walks.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0001</span>.</p></div><h4 id="fieldset_0-19_16">PAN, bits [19:16]</h4><div class="field">
      <p>Privileged Access Never. Indicates support for the PAN bit in <a href="AArch32-cpsr.html">CPSR</a>, <a href="AArch32-spsr.html">SPSR</a>, and <a href="AArch32-dspsr.html">DSPSR</a> in AArch32 state. Defined values are:</p>
    <table class="valuetable"><tr><th>PAN</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>PAN not supported.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>PAN supported.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>PAN supported and <a href="AArch32-ats1cprp.html">ATS1CPRP</a> and <a href="AArch32-ats1cpwp.html">ATS1CPWP</a> instructions supported.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p><span class="xref">FEAT_PAN</span> implements the functionality identified by the value <span class="binarynumber">0b0001</span>.</p>
<p><span class="xref">FEAT_PAN2</span> implements the functionality added by the value <span class="binarynumber">0b0010</span>.</p>
<p>In Armv8.1, the value <span class="binarynumber">0b0000</span> is not permitted.</p>
<p>From Armv8.2, the only permitted value is <span class="binarynumber">0b0010</span>.</p></div><h4 id="fieldset_0-15_12">MaintBcst, bits [15:12]</h4><div class="field">
      <p>Maintenance Broadcast. Indicates whether Cache, TLB, and branch predictor operations are broadcast. Defined values are:</p>
    <table class="valuetable"><tr><th>MaintBcst</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Cache, TLB, and branch predictor operations only affect local structures.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Cache and branch predictor operations affect structures according to shareability and defined behavior of instructions. TLB operations only affect local structures.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>Cache, TLB, and branch predictor operations affect structures according to shareability and defined behavior of instructions.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0010</span>.</p></div><h4 id="fieldset_0-11_8">BPMaint, bits [11:8]</h4><div class="field">
      <p>Branch Predictor Maintenance. Indicates the supported branch predictor maintenance operations in an implementation with hierarchical cache maintenance operations. Defined values are:</p>
    <table class="valuetable"><tr><th>BPMaint</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>None supported.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td><p>Supported branch predictor maintenance operations are:</p>
<ul>
<li>Invalidate all branch predictors.
</li></ul></td></tr><tr><td class="bitfield">0b0010</td><td><p>As for <span class="binarynumber">0b0001</span>, and adds:</p>
<ul>
<li>Invalidate branch predictors by VA.
</li></ul></td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0010</span>.</p></div><h4 id="fieldset_0-7_4">CMaintSW, bits [7:4]</h4><div class="field">
      <p>Cache Maintenance by Set/Way. Indicates the supported cache maintenance operations by set/way, in an implementation with hierarchical caches. Defined values are:</p>
    <table class="valuetable"><tr><th>CMaintSW</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>None supported.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td><p>Supported hierarchical cache maintenance instructions by set/way are:</p>
<ul>
<li>Invalidate data cache by set/way.
</li><li>Clean data cache by set/way.
</li><li>Clean and invalidate data cache by set/way.
</li></ul></td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0001</span>.</p>
<p>In a unified cache implementation, the data cache maintenance operations apply to the unified caches.</p></div><h4 id="fieldset_0-3_0">CMaintVA, bits [3:0]</h4><div class="field">
      <p>Cache Maintenance by Virtual Address. Indicates the supported cache maintenance operations by VA, in an implementation with hierarchical caches. Defined values are:</p>
    <table class="valuetable"><tr><th>CMaintVA</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>None supported.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td><p>Supported hierarchical cache maintenance operations by VA are:</p>
<ul>
<li>Invalidate data cache by VA.
</li><li>Clean data cache by VA.
</li><li>Clean and invalidate data cache by VA.
</li><li>Invalidate instruction cache by VA.
</li><li>Invalidate all instruction cache entries.
</li></ul></td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0001</span>.</p>
<p>In a unified cache implementation, data cache maintenance operations apply to the unified caches, and the instruction cache maintenance instructions are not implemented.</p></div><div class="access_mechanisms"><h2>Accessing ID_MMFR3</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRC{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b000</td><td>0b0000</td><td>0b0001</td><td>0b111</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T0 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T0 == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.TID3 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HCR.TID3 == '1' then
        AArch32.TakeHypTrapException(0x03);
    else
        R[t] = ID_MMFR3;
elsif PSTATE.EL == EL2 then
    R[t] = ID_MMFR3;
elsif PSTATE.EL == EL3 then
    R[t] = ID_MMFR3;
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:05; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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